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System Level Modelling and AMS Verification

 
System Level Modelling and AMS Verification
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YongaTek can give modelling services for your System and/or Analog domain, execute Analog Mixed Signal verification on your Mixed Signal IC:
System Level modelling and simulation by MATLAB, Simulink, C++
Analog block level modelling by VHDL, Verilog, VHDL-RN, VHDL-AMS, Verilog-AMS
Analog Mixed Signal Verification execution
Directed testing
Assertion based
Full Interconnect testing between Analog and Digital domains